View CS8406-IZ_336612.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CS8406
192 kHz Digital Audio Interface Transmitter
Features
Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF compatible transmitter +3.3 V or 5.0 V Digital Supply (VD) +3.3 V or 5.0 V Digital Interface (VL) On-chip Channel Status and User bit buffer memories allow block sized updates Flexible 3-wire serial digital audio input port Up to 192 kHz frame rate Microcontroller write access to Channel Status and User bit data On-chip differential line driver Generates CRC codes and parity bits Standalone mode allows use without a microcontroller 28-pin SOIC/TSSOP package
General Description
The CS8406 is a monolithic CMOS device which encodes and transmits audio data according to the AES3, IEC60958, S/PDIF, or EIAJ CP1201. The CS8406 accepts audio and digital data, which is then multiplexed, encoded and driven onto a cable. The audio data is input through a configurable, 3-wire input port. The channel status and user bit data are input through an SPI or IC microcontroller port, and may be assembled in block sized buffers. For systems with no microcontroller, a stand alone mode allows direct access to channel status and user bit data pins. Target applications include A/V Receivers, CD-R, DVD receivers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems. ORDERING INFORMATION CS8406-CS CS8406-CZ CS8406-IS CS8406-IZ CS8406-DS CS8406-DZ CDB8416 28-pin SOIC -10 to +70C 28-pin TSSOP -10 to +70C 28-pin SOIC -40 to +85C 28-pin TSSOP -40 to +85C 28-pin SOIC -40 to +85C 28-pin TSSOP -40 to +85C Evaluation Board
I
VD
VL
GND
RXP
ILRCK ISCLK SDIN
Serial Audio Input
Misc. Control
H/S
C & U bit Data Buffer
AES3 S/PDIF Encoder
TXP
Driver
TXN
TCBL
Control Port & Registers
Output Clock Generator
RST
U
SDA/ SCL/ AD1/ AD0/ AD2 INT CDOUT CCLK CDIN CS
OMCK
www.cirrus.com
Copyright Cirrus Logic, Inc. 2004 (All Rights Reserved)
JUL `04 DS580F1 1
(c)
CS8406
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 SPECIFIED OPERATING CONDITIONS ................................................................................. 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5 DC ELECTRICAL CHARACTERISTICS................................................................................... 6 DIGITAL INPUT CHARACTERISTICS ..................................................................................... 6 DIGITAL INTERFACE SPECIFICATIONS................................................................................ 6 TRANSMITTER CHARACTERISTICS ..................................................................................... 6 SWITCHING CHARACTERISTICS .......................................................................................... 7 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS................................................. 7 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE...................................... 9 SWITCHING CHARACTERISTICS - CONTROL PORT - IC MODE..................................... 10 2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 11 3. GENERAL DESCRIPTION ..................................................................................................... 13 3.1 AES3 and S/PDIF Standards Documents ........................................................................ 13 4. THREE-WIRE SERIAL INPUT AUDIO PORT ........................................................................ 14 5. AES3 TRANSMITTER ............................................................................................................ 16 5.1 Transmitted Frame and Channel Status Boundary Timing .............................................. 16 5.2 TXN and TXP Drivers ...................................................................................................... 16 5.3 Mono Mode Operation ..................................................................................................... 17 6. CONTROL PORT DESCRIPTION .......................................................................................... 19 6.1. SPI Mode ........................................................................................................................ 19 6.2. IC Mode ......................................................................................................................... 20 6.3. Memory Address Pointer (MAP) ..................................................................................... 21 6.3.1. Memory Address Pointer (MAP) Register Detail ........................................... 21 6.3.2. INCR (Auto Map Increment Enable) .................................................................. 21 6.3.3. MAP6-0 (Memory Address Pointer) ................................................................... 21 7. CONTROL PORT REGISTER SUMMARY ............................................................................. 22 8. CONTROL PORT REGISTER BIT DEFINITIONS .................................................................. 23 8.1 Control 1 (01h) .................................................................................................................. 23 8.2 Control 2 (02h) .................................................................................................................. 24 8.3 Data Flow Control (03h).................................................................................................... 24 8.4 Clock Source Control (04h)............................................................................................... 25 8.5 Serial Audio Input Port Data Format (05h)........................................................................ 25 8.6 Interrupt 1 Status (07h) (Read Only)................................................................................. 26 8.7 Interrupt 2 Status (08h) (Read Only)................................................................................. 27 8.8 Interrupt 1 Mask (09h)....................................................................................................... 27 8.9 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh) ......................................... 27 8.10 Interrupt 2 Mask (0Ch) .................................................................................................... 27 8.11 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)....................................... 28 8.12 Channel Status Data Buffer Control (12h) ...................................................................... 28 8.13 User Data Buffer Control (13h) ....................................................................................... 29 8.14 Channel Status bit or User bit Data Buffer (20h - 37h) ................................................... 29 8.15 CS8406 I.D. and Version Register (7Fh) (Read Only).................................................... 29 9. PIN DESCRIPTION - SOFTWARE MODE .......................................................................... 30 10. HARDWARE MODE ............................................................................................................. 32 10.1 Channel Status, User and Validity Data ......................................................................... 32 10.2 Serial Audio Port ............................................................................................................ 33 11. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 34 12. APPLICATIONS .................................................................................................................... 36 12.1 Reset, Power Down and Start-up .................................................................................. 36 12.2 ID Code and Revision Code .......................................................................................... 36
2
DS580F1
CS8406
12.3 Power Supply, Grounding, and PCB layout ................................................................... 36 12.4 Synchronization of Multiple CS8406s ............................................................................ 36 PACKAGE DIMENSIONS .................................................................................................. 37 APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS ...... 39 14.1 AES3 Transmitter External Components ....................................................................... 39 14.2 Isolating Transformer Requirements ............................................................................. 39 APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 40 15.1 AES3 Channel Status(C) Bit Management .................................................................... 40 15.1.1 Accessing the E buffer ...................................................................................... 40 15.1.2 Serial Copy Management System (SCMS) ....................................................... 41 15.1.3 Channel Status Data E Buffer Access .............................................................. 41 15.2 AES3 User (U) Bit Management .................................................................................... 42 15.2.1 Mode 1: Transmit All Zeros ............................................................................... 42 15.2.2 Mode 2: Block Mode ......................................................................................... 42 REVISION HISTORY ............................................................................................................ 43
13. 14.
15.
16.
DS580F1
3
CS8406
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing....................................................................................... 8 Figure 2. Audio Port Slave Mode and Data Input Timing ................................................................ 8 Figure 3. SPI Mode timing ............................................................................................................... 9 Figure 4. IC Mode timing .............................................................................................................. 10 Figure 5. Recommended Connection Diagram for Software Mode............................................... 11 Figure 6. Recommended Connection Diagram for Hardware Mode ............................................. 12 Figure 7. Serial Audio Input Example Formats.............................................................................. 15 Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data .............................................. 18 Figure 9. Control Port Timing in SPI Mode.................................................................................... 19 Figure 10. Control Port Timing, IC Slave Mode Write .................................................................. 20 Figure 11. Control Port Timing, IC Slave Mode Read .................................................................. 20 Figure 12. Hardware Mode Data Flow .......................................................................................... 32 Figure 13. Professional Output Circuit .......................................................................................... 39 Figure 14. Consumer Output Circuit (VL = 5.0 V) ......................................................................... 39 Figure 15. TTL/CMOS Output Circuit ............................................................................................ 39 Figure 16. Channel Status Data Buffer Structure .......................................................................... 40 Figure 17. Flowchart for Writing the E Buffer ................................................................................ 41
LIST OF TABLES
Table 1. Control Register Map Summary ...................................................................................... 22 Table 2. Hardware Mode COPY/C and ORIG pin functions.......................................................... 33 Table 3. Hardware Mode Serial Audio Port Format Selection....................................................... 33 Table 4. Hardware Mode OMCK Clock Ratio Selection ................................................................ 33 Table 5. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode ............................................................................... 33 Table 6. Revision History .............................................................................................................. 43
4
DS580F1
CS8406
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25C.)
SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V)
Parameter Power Supply Voltage Ambient Operating Temperature: `-CS' & `-CZ' `-IS', `-IZ', `-DS', & `-DZ' Symbol VD VL TA TA Min 3.14 3.14 -10 -40 Typ 3.3 or 5.0 3.3 or 5.0 Max 5.25 5.25 +70 +85 Units V V C C
ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.)
Parameter Power Supply Voltage Input Current, Any Pin Except Supplies Input Voltage Ambient Operating Temperature (power applied) Storage Temperature (Note 1) Symbol VD, VL Iin Vin TA Tstg Min -0.3 -55 -65 Max 6.0 10 VL + 0.3 125 150 Units V mA V C C
Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up.
DS580F1
5
CS8406
DC ELECTRICAL CHARACTERISTICS
Parameters Power-down Mode (Note 2) Supply Current in power down VD = 3.3 V VD = 5.0 V VL = 3.3 V VL = 5.0 V VD = 3.3 V VD = 5.0 V VL = 3.3 V VL = 5.0 V VD = 3.3 V VD = 5.0 V VL = 3.3 V VL = 5.0 V ID ID IL IL ID ID IL IL ID ID IL IL 20 40 0 0 1.9 3.5 6.5 10.6 7.6 12.7 7.2 12 A A A A mA mA mA mA mA mA mA mA (GND = 0 V; all voltages with respect to 0 V.) Symbol Min Typ Max Units
Normal Operation (Note 3) Supply Current at 48 kHz frame rate (Note 4)
Supply Current at 192 kHz frame rate (Note 4)
Notes: 2. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 3. Normal operation is defined as RST = HI. 4. Assumes that no inputs are left floating. It is recommended that all digital inputs be driven high or low at all times.
DIGITAL INPUT CHARACTERISTICS
Parameters Input Leakage Current Input Hysteresis (all inputs except OMCK) Symbol Iin Min Typ 0.25 Max 0.5 Units A V
DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to 0 V.)
Parameters High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN High-Level Output Voltage, TXP, TXN Low-Level Output Voltage, TXP, TXN High-Level Input Voltage Low-Level Input Voltage (21 mA at VL = 5.0 V) (15 mA at VL = 3.3 V) (21 mA at VL = 5.0 V) (16 mA at VL = 3.3 V) VD = 5.0 V VD = 3.3 V VD = 5.0 V VD = 3.3 V VIH VIL Symbol VOH VOL Min VL - 1.0 VL - 0.7 VL - 0.7 2.75 2.0 -0.3 -0.3 Max 0.4 VL VL 0.7 0.7 VL + 0.3 VL + 0.3 0.8 0.8 Units V V V V V V V V V V
TRANSMITTER CHARACTERISTICS
Parameters TXP Output Resistance TXN Output Resistance VL = 5.0 V VL = 3.3 V VL = 5.0 V VL = 3.3 V Symbol RTXP RTXN Typ 26.5 33.5 26.5 33.5 Units
6
DS580F1
CS8406
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C L = 20 pF) Parameter RST pin Low Pulse Width OMCK Frequency for OMCK = 512*Fs OMCK Low and High Width for OMCK = 512*Fs OMCK Frequency for OMCK = 384*Fs OMCK Low and High Width for OMCK = 384*Fs OMCK Frequency for OMCK = 256*Fs OMCK Low and High Width for OMCK = 256*Fs OMCK Frequency for OMCK = 128*Fs OMCK Low and High Width for OMCK = 128*Fs Frame Rate AES3 Transmitter Output Jitter Symbol Min 200 4.1 4.1 3.1 6.1 2.0 8.1 1.0 18.3 8 Typ 200 Max 98.4 73.8 49.2 24.6 192 Units s MHz ns MHz ns MHz ns MHz ns kHz ps
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C L = 20 pF) Parameter SDIN Setup Time Before ISCLK Active Edge SDIN Hold Time After ISCLK Active Edge (Note 5) (Note 5) (Note 5) (Note 6) Symbol tds tdh tsmd tlmd Min 10 8 0 0 tsckw tsckl tsckh (Note 7) (Note 8) tlrckd tlrcks 36 14.4 14.4 10 10 Typ 50 Max 17 16 Units ns ns ns ns % ns ns ns ns ns
Master Mode OMCK to ISCLK active edge delay
OMCK to ILRCK delay ISCLK and ILRCK Duty Cycle
Slave Mode ISCLK Period
ISCLK Input Low Width ISCLK Input High Width ISCLK Active Edge to ILRCK Edge ILRCK Edge Setup Before ISCLK Active Edge
Notes: 5. The active edge of ISCLK is programmable in Software mode. 6. The polarity of ILRCK is programmable in Software mode. 7. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed. 8. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.
DS580F1
7
CS8406
ISCLK (output)
ILRCK (input)
t lrckd
ISCLK (input)
t lrcks
t sckh
t sckl
ILRCK (output) t smd t OMCK (input) lmd
t sckw SDIN t ds t dh
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing
8
DS580F1
CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C L = 20 pF) Parameter CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 12) (Note 12) (Note 11) (Note 10) (Note 9) Symbol fsck tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Min 0 1.0 20 66 40 15 Typ Max 6.0 50 25 25 100 100 Units MHz s ns ns ns ns ns ns ns ns ns ns
MAX ((1/256 FS + 8), 66)
Notes: 9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is dictated by the timing requirements necessary to access the Channel Status and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. 10. Tsch must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns. 11. Data must be held for sufficient time to bridge the transition time of CCLK. 12. For fsck < 1 MHz.
CS t css CCLK t r2 CDIN t dsu t dh t f2 t scl t sch t csh
t pd
CDOUT
Figure 3. SPI Mode timing
DS580F1
9
CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - IC MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C L = 20 pF) Parameter SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup Time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition (Note 13) Symbol fscl tbuf thdst tlow thigh tsust thdd tsud tr tf tsusp Min 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Typ Max 100 1000 300 Units kHz s s s s s s ns ns ns s
13. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Stop SDA t buf SCL
Start
Repeated Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 4. IC Mode timing
10
DS580F1
CS8406
2. TYPICAL CONNECTION DIAGRAMS
+3.3 V or +5.0 V 0.1 F +3.3 V or +5.0 V 0.1 F
VD AES3 / S/PDIF Source Serial Audio Source Clock Source and Control RXP ILRCK ISCLK SDIN OMCK
VL
CS8406
TXP TXN
Transmission Interface
Microcontroller
AD0 / CS AD1 / CDIN AD2 SCL / CCLK SDA / CDOUT RST INT TCBL GND To/from other CS8406's
U 47k
User Data Source
H/S
Figure 5. Recommended Connection Diagram for Software Mode
DS580F1
11
CS8406
+3.3 V or +5.0 V 0.1 F
+3.3 V or +5.0 V 0.1 F
VD Serial Audio Source Clock Source and Control ILRCK ISCLK SDIN OMCK
VL H/S
CS8406
TXP TXN
Transmission Interface
Hardware Control
HWCK1 HWCK0 SFMT0 SFMT1 APMS TCBLD RST CEN EMPH AUDIO ORIG TCBL
COPY/C
C Data Source User Data Source 47k
U
V 47k GND
Validity Source
To/from other CS8406's
Figure 6. Recommended Connection Diagram for Hardware Mode
12
DS580F1
CS8406
3. GENERAL DESCRIPTION
The CS8406 is a monolithic CMOS device which encodes and transmits audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8406 accepts audio, channel status and user data, which is then multiplexed, encoded, and driven onto a cable. The audio data is input through a configurable, 3-wire input port. The channel status bits and user bit data are input through an SPI or IC Mode microcontroller port and may be assembled in separate block sized buffers. For systems with no microcontroller, a stand alone mode allows direct access to channel status and user data input pins. Target applications include CD-R, DAT, DVD, MD and VTR equipment, mixing consoles, digital audio transmission equipment, high quality A/D converters, effects processors, set-top TV boxes, and computer audio systems. Figure 5 shows the supply and external connections to the CS8406 when configured for operation with a microcontroller. Figure 6 shows the supply and external connections to the CS8406 when configured for operation without a microcontroller.
3.1
AES3 and S/PDIF Standards Documents
This data sheet assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3 and IEC60958 specifications on hand for easy reference. The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org or www.ansi.org. Obtain the latest IEC60958 standard from ANSI or from the International Electrotechnical Commission at www.iec.ch. The latest EIAJ CP-1201 standard is available from the Japanese Electronics Bureau. Application Note 22: Overview of Digital Audio Interface Data Structures contains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the standards. The paper An Understanding and Implementation of the SCMS Serial Copy Management System for Digital Audio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is available from the AES as reprint 3518.
DS580F1
13
CS8406
4. THREE-WIRE SERIAL INPUT AUDIO PORT
A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the attached device through the control registers. The following parameters are adjustable: * * * * * * * Master or slave Serial clock frequency Audio data resolution Left or right justification of the data relative to left/right clock Optional one-bit cell delay of the first data bit Polarity of the bit clock Polarity of the left/right clock. (By setting the appropriate control bits, many formats are possible).
Figure 7 shows a selection of common input formats with the corresponding control bit settings. In master mode, the left/right clock and the serial bit clock are outputs, derived from the OMCK input pin master clock. In slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the OMCK master clock, but the serial bit clock can be asynchronous and discontinuous if required. The left/right clock should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to clock all the data bits.
14
DS580F1
CS8406
Left ILRCK Left ISCLK Justified SDIN (In)
Right
MSB
LSB
MSB
LSB
MSB
IS (In)
2
ILRCK ISCLK SDIN
Left
Right
MSB
LSB
MSB
LSB
MSB
ILRCK Right ISCLK Justified (In) SDIN
Left
Right
LSB
MSB
LSB
MSB
LSB
SIMS*
SISF*
SIRES[1:0]*
SIJUST*
SIDEL*
SISPOL*
SILRPOL*
Left Justified IS Right Justified
X X X
X X X
00+ 00+ XX
0 0 1
0 1 0
0 0 0
0 1 0
X = don't care to match format, but does need to be set to the desired setting + IS can accept an arbitrary number of bits, determined by the number of ISCLK cycles * See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 7. Serial Audio Input Example Formats
DS580F1
15
CS8406
5. AES3 TRANSMITTER
The CS8406 includes an AES3 digital audio transmitter. A comprehensive buffering scheme provides write access to the channel status and user data. This buffering scheme is described in Appendix B: Channel Status and User Data Buffer Management. The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and bi-phase mark encoded. The resulting bit stream is driven to an output connector either directly or through a transformer. The transmitter is clocked from the clock input pin, OMCK. If OMCK is asynchronous to the data source, an interrupt bit (TSLIP) is provided that will go high every time a data sample is dropped or repeated. The channel status (C) and user (U) bits in the transmitted data stream are taken from storage areas within the CS8406. The user can manually access the internal storage or configure the CS8406 to run in one of several automatic modes. Appendix B: Channel Status and User Data Buffer Management provides detailed descriptions of each automatic mode and describes methods of manually accessing the storage areas. The transmitted user bit data can optionally be input through the U pin, under the control of a control port register bit. Figure 8 shows the C/U/V timing requirements.
5.1
Transmitted Frame and Channel Status Boundary Timing
The TCBL pin is used to control or indicate the start of transmitted channel status block boundaries and may be an input or an output. In some applications, it may be necessary to control the precise timing of the transmitted AES3 frame boundaries. This may be achieved in two ways: a) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well as a new channel status block start. b) If the serial audio input port is in slave mode and TCBL is set to output, the start of the A channel sub-frame will be aligned with the leading edge of ILRCK.
5.2
TXN and TXP Drivers
The line drivers are low skew, low impedance, differential outputs capable of driving cables directly. Both drivers are set to ground during reset (RST = LOW), when no AES3 transmit clock is provided, and optionally under the control of a register bit. The CS8406 also allows immediate muting of the AES3 transmitter audio data through a control register bit. External components are used to terminate and isolate the external cable from the CS8406. These components are detailed in "Appendix A: External AES3/SPDIF/IEC60958 Transmitter Components" on page 39.
16
DS580F1
CS8406
5.3 Mono Mode Operation
An alternate method for transmitting an AES3 192 kHz sample rate stream is mono mode. Mono mode is implemented by using the two sub-frames in a 96 kHz biphase encoded stream to carry consecutive samples of a single channel of a 192 kHz PCM stream (i.e. a mono signal). This allows older equipment, whose AES3 transmitters and receivers are not rated for 192 kHz frame rate operation, to handle 192 kHz sample rate information. In this mono mode, two AES3 cables and two CS8406's are needed for stereo data transfer. The CS8406 is set to mono mode by the MMT control bit. In mono mode, the input port will run at the audio sample rate (Fs), while the AES3 transmitter frame rate will be at Fs/2. Consecutive left or right channel serial audio data samples may be selected for transmission on the A and B sub-frames, and the channel status block transmitted is also selectable. Using mono mode is only necessary if the incoming audio sample rate is already at 192 kHz and contains both left and right audio data words. The "mono mode" AES3 output stream may also be achieved by keeping the CS8406 in normal stereo mode, and placing consecutive audio samples in the left and right positions in an incoming 96 kHz word rate data stream. Figure 8 shows the C/U/V timing requirements.
DS580F1
17
CS8406
TCBL (In/Output) VLRCK V/C/U (Input)
Tth
Tsetup VCU[0]
Thold VCU[1] VCU[2] VCU[3] VCU[4]
SDIN (Input) TXP(N) (Output) Z
Data [4]
Data [5]
Data [6]
Data [7]
Data [8]
Data [0]
Y
Data [1]
X
Data [2]
Y
Data [3]
X
Data [4]
AES3 Transmitter in Stereo mode
Tsetup 7.5% AES3 frame time Thold = 0 Tth > 3 OMCK clocks, if TCBL is Input
TCBL (In/Output) VLRCK
Tth
U (Input) SDIN (Input) TXP(N) (Output) Z Data [4] Data [5]
U[0]
U[2]
Data [6]
Data [7]
Data [8]
Data [0]*
Y
Data [2]*
X
Data [4]*
* Assume MMTLR = 0 TXP(N) (Output) Z Data [1]* Y Data [3]* X Data [5]*
* Assume MMTLR = 1 Tsetup 15% AES3 frame time Thold = 0 Tth > 3 OMCK clocks, if TCBL is Input
AES3 Transmitter in Mono mode
*VLRCK is a virtual word clock, which may not exist, and is used to illustrate the CUV timing. *VLRCK duty cycle is 50%. *In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, VLRCK frequency = 2xAES3 frame rate. *If the serial audio input port is on slave mode and TCBL is an output, then VLRCK = ILRCK if SILRPOL = 0 and VLRCK = ILRCK if SILRPOL =1. *If the serial audio input port is in master mode and TCBL is an input, then VLRCK = ILRCK if SILRPOL = 0 and VLRCK = ILRCK if SILRPOL =1.
Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data
18
DS580F1
CS8406
6. CONTROL PORT DESCRIPTION The control port is used to access the registers, allowing the CS8406 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
The control port has 2 modes: SPI and IC, with the CS8406 acting as a slave device. SPI mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. IC mode is selected by connecting the AD0/CS pin through a resistor to VL or GND, thereby permanently selecting the desired AD0 bit address state.
6.1. SPI Mode In SPI mode, CS is the CS8406 chip select signal, CCLK is the control port bit clock (input into the CS8406 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 9 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 0010000. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired.
There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set
CS
CCLK C H IP ADDRESS C D IN C H IP AD D R ESS LSB b y te n MSB LSB MSB LSB
MAP R/W MSB
DATA
0010000
0010000
R/W
b y te 1
High Impedance
CDOUT
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 9. Control Port Timing in SPI Mode
DS580F1
19
CS8406
the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecutively.
6.2. IC Mode In IC mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0, AD1, and AD2 form the three least significant bits of the chip address and should be connected through a resistor to VL or GND as desired.
The signal timings for a read and write cycle are shown in Figure 10 and Figure 11. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS8406 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The upper 4 bits of the 7-bit address field are fixed at 0010. To communicate with a CS8406, the chip address field, which is the first byte sent to the CS8406, should match 0010 followed by the settings of the AD2, AD1, and AD0 pins. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit (ACK). The ACK bit is output from the CS8406 after each input byte is read, and is input to the CS8406 from the microcontroller after each transmitted byte.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
0 0 1 0 AD2 AD1 AD0 0
6
5
4
3
ACK START
ACK
ACK
ACK STOP
Figure 10. Control Port Timing, IC Slave Mode Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0
CHIP ADDRESS (READ)
0 0 1 0 AD2 AD1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
0 0 1 0 AD2 AD1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 11. Control Port Timing, IC Slave Mode Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 11, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
20
DS580F1
CS8406
Send start condition. Send 0010xxx0 (chip address & write operation). Receive acknowledge (ACK) bit. Send MAP byte, auto increment off. Receive ACK bit. Send stop condition, aborting write. Send start condition. Send 0010xxx(chip address & read operation). Receive ACK bit. Receive byte, contents of selected register. Send no acknowledge (NO ACK) bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
6.3. Memory Address Pointer (MAP)
6.3.1.
7 INCR
Memory Address Pointer (MAP) Register Detail
6 MAP6 5 MAP5 4 MAP4 3 MAP3 2 MAP2 1 MAP1 0 MAP0
6.3.2.
INCR (Auto Map Increment Enable) Default = `0' 0 - Disabled, the MAP will stay constant for successive writes 1 - Enabled, the MAP will auto increment after each byte is written, allowing block reads or writes of successive registers MAP6-0 (Memory Address Pointer) Default = `0000000'
6.3.3.
DS580F1
21
CS8406
7. CONTROL PORT REGISTER SUMMARY
Function 7 6 5 4 3 2 1 0
Addr (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F-11 12 13 1D-1F 20-37 7F
Reserved 0 0 0 0 0 0 Control 1 0 VSET 0 MUTEAES 0 INT1 Control 2 0 0 0 0 0 MMT Data Flow Control 0 TXOFF AESBP 0 0 0 Clock Source Control 0 RUN CLK1 CLK0 0 0 Serial Input Format SIMS SISF SIRES1 SIRES0 SIJUST SIDEL Reserved 0 0 0 0 0 0 Interrupt 1 Status TSLIP 0 0 0 0 0 Interrupt 2 Status 0 0 0 0 0 EFTU Interrupt 1 Mask TSLIPM 0 0 0 0 0 Interrupt 1 Mode (MSB) TSLIP1 0 0 0 0 0 Interrupt 1 Mode (LSB) TSLIP0 0 0 0 0 0 Interrupt 2 Mask 0 0 0 0 0 EFTUM Interrupt 2 Mode (MSB) 0 0 0 0 0 EFTU1 Interrupt 2 Mode (LSB) 0 0 0 0 0 EFTU0 Reserved 0 0 0 0 0 0 CS Data Buffer Control 0 0 BSEL 0 0 EFTCI U Data Buffer Control 0 0 0 UD UBM1 UBM0 Reserved 0 0 0 0 0 0 C or U Data Buffer ID and Version ID3 ID2 ID1 ID0 VER3 VER2
Table 1. Control Register Map Summary
0 0 INT0 TCBLD MMCST MMTLR 0 0 0 0 SISPOL SILRPOL 0 0 EFTC 0 0 0 EFTCM 0 EFTC1 0 EFTC0 0 0 0 0 0 0 0 0 0 CAM 0 0 EFTUI 0 0 VER1 VER0
Notes:
Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8406.
22
DS580F1
CS8406
8.
8.1
7
0
CONTROL PORT REGISTER BIT DEFINITIONS
Control 1 (01h)
6
VSET
5
0
4
MUTEAES
3
0
2
INT1
1
INT0
0
TCBLD
VSET - Transmitted Validity bit level
Default = `0' 0 - Indicates data is valid, linear PCM audio data 1 - Indicates data is invalid or not linear PCM audio data
MUTEAES - Mute control for the AES transmitter output
Default = `0' 0 - Not Muted 1 - Muted
INT1:0 - Interrupt output pin (INT) control
Default = `00' 00 - Active high; high output indicates interrupt condition has occurred 01 - Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved
TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier
Default = `0' 0 - TCBL is an input 1 - TCBL is an output
DS580F1
23
CS8406
8.2
7
0
Control 2 (02h)
6
0
5
0
4
0
3
0
2
MMT
1
MMTCS
0
MMTLR
MMT - Select AES3 transmitter mono or stereo operation
Default = `0' 0 - Normal stereo operation 1 - Output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by MMTLR bit)
MMTCS - Select A or B channel status data to transmit in mono mode
Default = `0' 0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe 1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data.
MMTLR - Channel Selection for AES Transmitter mono mode
Default = `0' 0 - Use left channel input data for consecutive subframe outputs 1- Use right channel input data for consecutive subframe outputs
8.3
7
0
Data Flow Control (03h)
6
TXOFF
5
AESBP
4
0
3
0
2
0
1
0
0
0
The Data Flow Control register configures the flow of audio data. The output data should be muted prior to changing bits in this register to avoid transients.
TXOFF - AES3 Transmitter Output Driver Control
Default = `0 0 - AES3 transmitter output pin drivers normal operation 1 - AES3 transmitter output pin drivers drive to 0 V.
AESBP - AES3 bypass mode selection
Default = `0' 0 - Normal operation 1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL threshold digital input.
24
DS580F1
CS8406
8.4
7
0
Clock Source Control (04h)
6
RUN
5
CLK1
4
CLK0
3
0
2
0
1
0
0
0
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, various Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8406 to be placed in a "powered down" low current consumption, state.
Default = `0' 0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port registers are operational, allowing registers to be read or changed. Reading and writing the U and C data buffers is not possible. Power consumption is low. 1 - Normal part operation. This bit must be set to 1 to allow the CS8406 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1.
CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector. If these bits are changed during normal operation, then always stop the CS8406 first (RUN = 0), write the new value, then start the CS8406 (RUN = 1).
Default = `00' 00 - OMCK frequency is 256*Fs 01 - OMCK frequency is 384*Fs 10 - OMCK frequency is 512*Fs 11 - OMCK frequency is 128*Fs
8.5
7
Serial Audio Input Port Data Format (05h)
6
SISF
5
SIRES1
4
SIRES0
3
SIJUST
2
SIDEL
1
SISPOL
0
SILRPOL
SIMS
SIMS - Master/Slave Mode Selector
Default = `0' 0 - Serial audio input port is in slave mode 1 - Serial audio input port is in master mode
SISF - ISCLK frequency (for master mode)
Default = `0' 0 - 64*Fs 1 - 128*Fs
SIRES1:0 - Resolution of the input data, for right-justified formats
Default = `00' 00 - 24-bit resolution 01 - 20-bit resolution 10 - 16-bit resolution 11 - Reserved
DS580F1
25
CS8406
SIJUST - Justification of SDIN data relative to ILRCK
Default = `0' 0 - Left-justified 1 - Right-justified
SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats
Default = `0' 0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (left justified mode) 1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge (IS mode)
SISPOL - ISCLK clock polarity
Default = `0' 0 - SDIN sampled on rising edges of ISCLK 1 - SDIN sampled on falling edges of ISCLK
SILRPOL - ILRCK clock polarity
Default = `0' 0 - SDIN data is for the left channel when ILRCK is high 1 - SDIN data is for the right channel when ILRCK is high
8.6
7
Interrupt 1 Status (07h) (Read Only)
6
0
5
0
4
0
3
0
2
0
1
EFTC
0
0
TSLIP
For all bits in this register, a `1' means the associated interrupt condition has occurred at least once since the register was last read. A `0' means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to `0', unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be `0' in this register. This register defaults to 00h.
TSLIP - AES3 transmitter source data slip interrupt
In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit will go high on receipt of a new TCBL signal.
EFTC - E to F C-buffer transfer interrupt.
The source for this bit is true during the E to F buffer transfer in the C bit buffer management process.
26
DS580F1
CS8406
8.7
7
0
Interrupt 2 Status (08h) (Read Only)
6
0
5
0
4
0
3
0
2
EFTU
1
0
0
0
For all bits in this register, a `1' means the associated interrupt condition has occurred at least once since the register was last read. A `0' means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to `0', unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be `0' in this register. This register defaults to 00h.
EFTU - E to F U-buffer transfer interrupt. (Block Mode only)
The source of this bit is true during the E to F buffer transfer in the U bit buffer management process.
8.8
7
Interrupt 1 Mask (09h)
6
0
5
0
4
0
3
0
2
0
1
EFTCM
0
0
TSLIPM
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in Interrupt 1 register. This register defaults to 00h.
8.9
7
Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)
6
0 0
5
0 0
4
0 0
3
0 0
2
0 0
1
EFTC1 EFTC0
0
0 0
TSLIP1 TSLIP0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These registers default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved
8.10
7
0
Interrupt 2 Mask (0Ch)
6
0
5
0
4
0
3
0
2
EFTUM
1
0
0
0
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in Interrupt 2 register. This register defaults to 00h.
DS580F1
27
CS8406
8.11
7
0 0
Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)
6
0 0
5
0 0
4
0 0
3
0 0
2
EFTU1 EFTU0
1
0 0
0
0 0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These registers default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved
8.12
7
0
Channel Status Data Buffer Control (12h)
6
0
5
BSEL
4
0
3
0
2
EFTCI
1
CAM
0
0
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = `0' 0 - Data buffer address space contains Channel Status data 1 - Data buffer address space contains User data Note: There are separate complete buffers for the Channel Status and User bits. This control bit determines which buffer appears in the address space.
EFTCI - E to F C-data buffer transfer inhibit bit.
Default = `0' 0 - Allow C-data E to F buffer transfers 1 - Inhibit C-data E to F buffer transfers
CAM - C-data buffer control port access mode bit
Default = `0' 0 - One byte mode 1 - Two byte mode
28
DS580F1
CS8406
8.13
7
0
User Data Buffer Control (13h)
6
0
5
0
4
UD
3
UBM1
2
UBM0
1
0
0
EFTUI
UD - User bit data source specifier
Default = `0' 0 - U Pin is the source of transmitted U data 1 - U data buffer is the source of transmitted U data
UBM1:0 - Sets the operating mode of the AES3 User bit manager
Default = `00' 00 - Transmit all zeros mode 01 - Block mode 10 - Reserved 11 - Reserved
EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only).
Default = `0' 0 - Allow U-data E to F buffer transfers 1 - Inhibit U-data E to F buffer transfers
8.14
Channel Status bit or User bit Data Buffer (20h - 37h)
Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block mode) is accessible through these register addresses.
8.15
7
CS8406 I.D. and Version Register (7Fh) (Read Only)
6
ID2
5
ID1
4
ID0
3
VER3
2
VER2
1
VER1
0
VER0
ID3
ID[3:0] - ID code for the CS8406. Permanently set to 1110 VER[3:0] = 0001 (revision A) VER[3:0] = 0010 (revision B)
DS580F1
29
CS8406
9. PIN DESCRIPTION - SOFTWARE MODE
SDA / CDOUT AD0 / CS AD2 RXP TEST VD TEST TEST RST TEST TEST ILRCK ISCLK SDIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
SCL / CCLK AD1 / CDIN TXP TXN H/S VL GND OMCK U INT TEST TEST TEST TCBL
VD VL GND RST
6 23 22 9
Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V. Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. Ground (Input) - Ground for I/O and core logic. Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8406 devices, where synchronization between devices is important. Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation of the CS8406, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. To select Software mode, this pin should be permanently tied to GND. Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled low while the CS8406 is in the reset state. Master Clock (Input) - The frequency can be set through the control port registers. Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. Serial Audio Data Port (Input) - Audio data serial input pin.
H/S
24
TXN TXP OMCK ISCLK ILRCK SDIN
25 26 21 13 12 14
30
DS580F1
CS8406
SDA/CDOUT 1 Serial Control Data I/O (IC Mode) / Data Out (SPI) (Input/Output) - In IC Mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI mode, CDOUT is the output data from the control port interface on the CS8406 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8406. In IC mode, SCL requires an external pull-up resistor to VL. Address Bit 0 (IC Mode) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8406 into SPI control port mode. With no falling edge, the CS8406 defaults to IC mode. In IC mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8406 Address Bit 1 (IC Mode) / Serial Control Data in (SPI) (Input) - In IC mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port interface. Address Bit 2 (IC Mode) (Input) - Determines the AD2 address bit for the control port in IC mode, and should be connected to GND or VL. If SPI mode is used, the AD2 pin should be connected to either GND or VL. Auxiliary AES3 Receiver Port (Input) - Input for an alternate, already AES3 coded, audio data source. Interrupt (Output) - Indicates key events during the operation of the CS8406. All bits affecting INT may be unmasked through bits in the control registers. Indication of the condition(s) that initiated an interrupt are readable in the control registers. The polarity of the INT output, as well as selection of a standard or open drain output, is set through a control register. Once set true, the INT pin goes false only after the interrupt status registers have been read and the interrupt status bits have returned to zero. Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block. User Data (Input) - May optionally be used to input User data for transmission by the AES3 transmitter, see Figure 4 for timing information. If not driven, a 47 k pull-down resistor is recommended for the U pin. If the U pin is driven by a logic level output, then a 100 series resistor is recommended. Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, however current consumption from VL will increase by 25 A per TEST pin that is left floating.
SCL/CCLK AD0/CS
28 2
AD1/CDIN AD2
27 3
RXP INT
4 19
TCBL
15
U
20
TEST
7 8 10 11 16 17 18
DS580F1
31
CS8406
10.HARDWARE MODE
The CS8406 has a hardware mode that allows the use of the device without a microcontroller. Hardware mode is selected by connecting the H/S pin to VL. The flexibility of the CS8406 is necessarily limited in hardware mode. Various pins change function as described in the hardware mode pin description section. The hardware mode data flow is shown in Figure 12. Audio data is input through the serial audio input port and routed to the AES3 transmitter.
10.1 Channel Status, User and Validity Data
The transmitted channel status, user and validity data can be input in two methods, determined by the state of the CEN pin. Mode A is selected when the CEN pin is low. In mode A, the user bit data and the validity bit are input through the U and V pins, clocked by both edges of ILRCK. The channel status data is derived from the state of the COPY/C, ORIG, EMPH, and AUDIO pins. Table 2 shows how the COPY/C and ORIG pins map to channel status bits. In consumer mode, the transmitted category code is set to General (00h). Mode B is selected when the CEN pin is high. In mode B, the channel status, user data bits and the validity bit are input serially through the COPY/C, U and V pins. Data is clocked into these pins at both edges of ILRCK. Figure 8 shows the timing requirements.
VL
RST
H/S
Output Clock Source
OMCK
TCBLD
ILRCK ISCLK
Serial Audio Input
AES3 Encoder & Tx
SDIN
TXP TXN TCBL
C, U, V Data Buffer
CEN U V
APMS SFMT1 SFMT0
COPY/C ORIG EMPH AUDIO
Power supply pins are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 12. Hardware Mode Data Flow
32
DS580F1
CS8406
The channel status block pin (TCBL) may be an input or an output, determined by the state of the TCBLD pin.
COPY/C 0 0 1 1 ORIG 0 1 0 1 Function
PRO=0, COPY=0, L=0 copyright PRO=0, COPY=0, L=1 copyright, pre-recorded PRO=0, COPY=1, L=0 non-copyright PRO=1
Table 2. Hardware Mode COPY/C and ORIG pin functions
10.2 Serial Audio Port
The serial audio input port data format is selected as shown in Table 3, and may be set to master or slave by the state of the APMS input pin. The OMCK clock ratio is selected as shown in Table 4. Table 5 describes the equivalent software mode, bit settings for each of the available formats. Timing diagrams are shown in Figure 7.
SFMT1 0 0 1 1
SFMT0 0 1 0 1
Function
Serial Input Format IF1 - Left Justified Serial Input Format IF2 - IS Serial Input Format IF3 - Right Justified, 24-bit data Serial Input Format IF4 - Right Justified, 16-bit data
Table 3. Hardware Mode Serial Audio Port Format Selection
HWCK1 0 0 1 1
HWCK0 0 1 0 1
Function
OMCK Frequency is 256*Fs OMCK Frequency is 128*Fs OMCK Frequency is 512*Fs OMCK Frequency is 256*Fs
Table 4. Hardware Mode OMCK Clock Ratio Selection
IF1 - Left Justified IF2 - IS IF3 - Right Justified, 24-bit data IF4 - Right Justified, 16-bit data
SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL 0 00 0 0 0 0 0 00 0 1 0 1 0 00 1 0 0 0 0 10 1 0 0 0
Table 5. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode
DS580F1
33
CS8406
11.PIN DESCRIPTION - HARDWARE MODE
COPY / C TEST EMPH SFMT0 SFMT1 VD TEST TEST RST APMS TCBLD ILRCK ISCLK SDIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
ORIG HWCK1 TXP TXN H/S VL GND OMCK HWCK0 AUDIO U V CEN TCBL
VD VL GND RST
6 23 22 9
Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V. Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. Ground (Input) - Ground for I/O and core logic. Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8406 devices, where synchronization between devices is important. Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation of the CS8406, and the method of accessing CS and U data. Hardware mode provides an alternate mode of operation, and access to CS and U data is provided by dedicated pins. To select Hardware mode, this pin should be permanently tied to VL. Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled low while the CS8406 is in the reset state. Master Clock (Input) - The frequency can be set through the HWCK[1:0] pins. Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. Serial Audio Data Port (Input) - Audio data serial input pin. Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See Table 3 on page 33.
H/S
24
TXN TXP OMCK ISCLK ILRCK SDIN SFMT0 SFMT1
25 26 21 13 12 14 4 5
34
DS580F1
CS8406
APMS HWCK0 HWCK1 TCBLD TCBL 10 20 27 11 15 Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL to set serial audio input port as a master or connected to GND to set the port as a slave. OMCK Clock Ratio Select (Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to VL or pull-down to GND is required to set the appropriate mode. See Table 4 on page 33. Transmit Channel Status Block Direction (Input) - Connect TCBLD to VL to set TCBL as an output. Connect TCBLD to GND to set TCBL as an input. Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block. C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low, hardware mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel status data. When CEN is high, hardware mode B is selected, where the COPY/C pin is used to enter serial channel status data. Validity Bit (Input) - In hardware modes A and B, the V pin input determines the state of the validity bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. User Data Bit (Input) - In hardware modes A and B, the U pin input determines the state of the user data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. COPY Channel Status Bit/C Bit (Input) - In hardware mode A (CEN = 0), the COPY/C and ORIG pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream, see Table 2 on page 33. In hardware mode B, the COPY/C pin becomes the direct C bit input data pin, which is sampled on both edges of LRCK. Pre-Emphasis Indicator (Input) - In hardware mode A (CEN = 0), the EMPH pin low sets the 3 emphasis channel status bits to indicate 50/15 s pre-emphasis of the transmitted audio data. If EMPH is high, then the three EMPH channel status bits are set to 000, indicating no pre-emphasis. Audio Channel Status Bit (Input) - In hardware mode A (CEN = 0), the AUDIO pin determines the state of the audio/non audio Channel Status bit in the outgoing AES3 data stream. ORIG Channel Status Bit Control (Input) - In hardware mode A (CEN = 0), the ORIG and COPY/C pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream, see Table 2 on page 33. Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, however current consumption from VL will increase by 25 A per TEST pin that is left floating.
CEN
16
V U COPY/C
17 18 1
EMPH
3
AUDIO ORIG
19 28
TEST
2 7 8
DS580F1
35
CS8406
12.APPLICATIONS 12.1 Reset, Power Down and Start-up
When RST is low, the CS8406 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are disabled. In Software mode when RST is high, the control port becomes operational and the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause the part to leave the low power state and begin operation. In Hardware mode when RST is high, the part will automatically leave the low power state and begin operation.
12.2 ID Code and Revision Code
The CS8406 has a register that contains a four-bit code to indicate that the addressed device is a CS8406. This is useful when other CS84XX family members are resident in the same or similar systems, allowing common software modules. The CS8406 four-bit revision level code is also available. This allows the software driver for the CS8406 to identify which revision of the device is in a particular system, and modify its behavior accordingly. To allow for future revisions, it is strongly recommended that the revision code is read into a variable area within the microcontroller, and used wherever appropriate as revision details become known.
12.3 Power Supply, Grounding, and PCB layout
The CS8406 operates from a VD = +3.3 V or +5.0 V and VL = +3.3 V or +5.0 V supply. These supplied may be set independently. Follow normal supply decoupling practices, see Figure 5 and Figure 6. The VD and VL supplies should be decoupled with a 0.1 F capacitor to GND to minimize AES3 transmitter induced transients. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as the CS8406 to minimize inductance effects, and all decoupling capacitors should be as close to the CS8406 as possible.
12.4 Synchronization of Multiple CS8406s
The AES3 transmitters of multiple CS8406s can be synchronized if all devices share the same master clock, TCBL, and RST signals. The TCBL pin is used to synchronize multiple CS8406 AES3 transmitters at the channel status block boundaries. One CS8406 must have its TCBL set to master; the others must be set to slave TCBL. Alternatively, TCBL can be derived from external logic, whereby all CS8406 devices should be set to slave TCBL.
36
DS580F1
CS8406
13. PACKAGE DIMENSIONS
28L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
DIM A A1 b C D E e H L
MIN 0.093 0.004 0.013 0.009 0.697 0.291 0.040 0.394 0.016 0
INCHES NOM 0.098 0.008 0.017 0.011 0.705 0.295 0.050 0.407 0.026 4
MAX 0.104 0.012 0.020 0.013 0.713 0.299 0.060 0.419 0.050 8
MIN 2.35 0.10 0.33 0.23 17.70 7.40 1.02 10.00 0.40 0
MILLIMETERS NOM 2.50 0.20 0.42 0.28 17.90 7.50 1.27 10.34 0.65 4
MAX 2.65 0.30 0.51 0.32 18.10 7.60 1.52 10.65 1.27 8
JEDEC #: MS-013
Controlling Dimension is Millimeters
DS580F1
37
CS8406
28L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03150 0.00748 0.378 BSC 0.248 0.169 -0.020 0 NOM -0.004 0.035 0.0096 0.382 BSC 0.2519 0.1732 0.026 BSC 0.024 4 MAX 0.47 0.006 0.04 0.012 0.386 BSC 0.256 0.177 -0.029 8 MIN -0.05 0.80 0.19 9.60 BSC 6.30 4.30 -0.50 0
MILLIMETERS NOM -0.10 0.90 0.245 9.70 BSC 6.40 4.40 0.65 BSC 0.60 4 MAX 1.20 0.15 1.00 0.30 9.80 BSC 6.50 4.50 -0.75 8
NOTE
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters.
Notes: 1."D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
38
DS580F1
CS8406
14.APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS
This section details the external components required to interface the AES3 transmitter to cables and fiber-optic components.
14.1 AES3 Transmitter External Components
The output drivers on the CS8406 are designed to drive both the professional and consumer interfaces. The AES3 and IEC60958-4 specifications call for a balanced output drive of 2-7 V peakto-peak into a 110 20% load with no cable attached. Using the circuit in Figure 13, the output of the transformer is short-circuit protected, has the proper source impedance, and provides a 5 V peak-to-peak signal into a 110 load. Lastly, the two output pins should be attached to an XLR connector with male pins and a female shell, and with pin 1 of the connector grounded. In the case of consumer use, the IEC60958-3 specification calls for an unbalanced drive circuit with an output impedance of 75 20% and a output drive level of 0.5 V peak-to-peak 20% when measured across a 75 load using no cable. The circuit shown in Figure 14 only uses the TXP pin and provides the proper output impedance and drive level using standard 1% resistors. If VL is set to +3.3 V, change 374 to 243 and change 90.9 to 107 . The connector for a consumer application would be an RCA phono socket. This circuit is also short circuit protected. The TXP pin may be used to drive TTL or CMOS gates as shown in Figure 15. This circuit may be used for optical connectors for digital audio since they usually have TTL or CMOS compatible inputs. This circuit is also useful when driving multiple digital audio outputs since RS422 line drivers have TTL compatible inputs.
14.2 Isolating Transformer Requirements
Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on transformer selection.
CS8406 TXP XLR TXN 110-(RTXP+RTXN)
CS8406 TXP
374-RTXP RCA Phono
90.9 TXN
1
Figure 13. Professional Output Circuit
CS8406 TXP
Figure 14. Consumer Output Circuit (VL = 5.0 V)
TTL or CMOS Gate TXN
Figure 15. TTL/CMOS Output Circuit
DS580F1
39
CS8406
15.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT
The CS8406 has a comprehensive channel status (C) and user (U) data buffering scheme which allows the user to manage the C and U data through the control port.
15.1 AES3 Channel Status(C) Bit Management
The CS8406 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these RAM buffers through the control port. The CS8406 manages the flow of channel status data at the block level, meaning that entire blocks of channel status information are buffered at the input, synchronized to the output timebase, and then transmitted. The buffering scheme involves a cascade of 2 block-sized buffers, named E and F, as shown in Figure 16. The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port address 20h) is the consumer/professional bit for channel status block A. The E buffer is accessible from the control port, allowing read and writing of the C data. The F buffer is used as the source of C data for the AES3 transmitter. The F buffer accepts block transfers from the E buffer.
A 8 -bits B 8 -b its
E
24 w o rds
F
Tran sm it D a ta Bu ffer
To AES3 Tra nsm itte r
C on tro l Port
Figure 16. Channel Status Data Buffer Structure
15.1.1 Accessing the E buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into the register space of the CS8406, through the control port. The user can modify the data to be transmitted by writing to the E buffer. The user can configure the interrupt enable register to cause interrupts to occur whenever "E to F" buffer transfers occur. This allows determination of the allowable time periods to interact with the E buffer. Also provided is an "E to F" inhibit bit. The "E to F" buffer transfer is disabled whenever the user sets this bit. This may be used whenever "long" control port interactions are occurring. A flowchart for reading and writing to the E buffer is shown in Figure 17. For writing, the sequence starts after a E to F transfer, which is based on the output timebase.
40
DS580F1
CS8406
If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calculated by the CS8406, and does not have to be written into the last byte of the block by the host microcontroller. This is also true if the channel status data is entered serially through the COPY/C pin when the part is in hardware mode.
E to F interrupt occurs Optionally set E to F inhibit
Write E data
If set, clear E to F inhibit
Wait for E to F transfer
Return
Figure 17. Flowchart for Writing the E Buffer
15.1.2 Serial Copy Management System (SCMS)
In software mode, the CS8406 allows read/modify/write access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to manipulate the Category Code, Copy bit and L bit appropriately. In hardware mode, the SCMS protocol can be followed by either using the COPY and ORIG input pins, or by using the C bit serial input pin. These options are documented in the hardware mode section of this data sheet.
15.1.3 Channel Status Data E Buffer Access
The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data, and the LS Byte is the B channel data (see Figure 16).
There are two methods of accessing this memory, known as one byte mode and two byte mode. The desired mode is selected through a control register bit.
15.1.3.1 One Byte mode
In many applications, the channel status blocks for the A and B channels will be identical. In this situation, if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will be the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. One byte mode takes advantage of the often identical nature of A and B channel status data. When reading data in one byte mode, a single byte is returned, which can be from channel A or B data, depending on a register control bit. If a write is being done, the CS8406 expects a single
DS580F1
41
CS8406
byte to be input to its control port. This byte will be written to both the A and B locations in the addressed word. One byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access time. If the control port's auto increment addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently.
15.1.3.2 Two Byte mode
There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8406 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be input to the CS8406's control port. The A channel status data is first, B channel status data second.
15.2 AES3 User (U) Bit Management
The CS8406 U bit manager has two operating modes: Mode 1. Transmit all zeros. Mode 2. Block mode.
15.2.1 Mode 1: Transmit All Zeros
Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents. This mode is intended for the user who wants the output U channel to contain no data.
15.2.2 Mode 2: Block Mode
Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered using 2 block-sized RAMs to perform the buffering. The user has access to the first buffer, denoted the E buffer, through the control port. It is the only mode in which the user can merge his own U data into the transmitted AES3 data stream. The U buffer access only operates in two byte mode, since there is no concept of A and B blocks for user data. The arrangement of the data is as followings: Bit15[A7] Bit14[B7] Bit13[A6] Bit12 [B6]...Bit1 [A0] Bit0[B0]. The arrangement of the data in the each byte is that the MSB is the first transmitted bit. The bit for the A subframe is followed by the bit for the B subframe.
42
DS580F1
CS8406
16. REVISION HISTORY
Release Date Changes
PP1 PP2 PP3
August 2002 May 2003 January 2004
1st Preliminary Release 2nd Preliminary Release -Corrected "OMCK Low and High Width for OMCK = 384*Fs" on page 7. -Corrected "Rise Time of Both SDA and SCL Lines" on page 10. -Corrected "Fall Time of Both SDA and SCL Lines" on page 10. -Added Note 13 on page 10. -Corrected Figure 6. "Recommended Connection Diagram for Hardware Mode" on page 12 -Revised "Control Port Description" on page 19 Final Release -Corrected "SDIN Setup Time Before ISCLK Active Edge" on page 7. -Corrected Note 5 on page 7. -Corrected Note 6 on page 7. -Added Figure 8. "AES3 Transmitter Timing for C, U, and V Pin Input Data" on page 18 -Corrected H/S pin description on page 34.
Table 6. Revision History
F1
July 2004
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IIMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. Purchase of IC Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips IC Patent Rights to use those components in a standard IC system.
DS580F1
43

▲Up To Search▲

Price & Availability of CS8406-IZ

	To Download CS8406-IZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .